The present invention relates in general to data processing systems, and in particular, to data transfer verification in hardware design simulations.
Advances in manufacturing technology, hardware design architectures, and development tools have allowed for the integration of many functions on to a single hardware design, for example, as an xe2x80x9csystem on a chip,xe2x80x9d which may be referred to as a core plus application-specific integrated circuit (ASIC) system. In such systems, it is common to integrate many design components using standardized bus interfaces within an integrated design which ultimately represents a single hardware solution. As a consequence of this increased level of function, peripherals that would typically be verified with the processor at the current level, via a system level bus, are now being integrated into the same xe2x80x9csiliconxe2x80x9d as a processor. As a result, several on-chip bus architectures have been developed to address the on-chip communication between processor cores and peripherals. Along with these bus architectures, simulation tools are being developed to test the function of logic macros with the on-chip bus interfaces.
Verification of logic designs includes testing that data is transferred properly within the system under test. Data is stored in memory elements, for example, caches, static memory, dynamic memory, and other systems storage elements. During the verification process, these memories must be initialized with data to verify read accesses by a master device. Also, the memory devices must be checked during and after a test is executed to ensure that data was properly transferred and stored when master devices perform write cycles within the system.
In simulating logic macros in a hardware system design, test data must be selected for transfer between components within the system. This data also must be varied between tasks, so that a logic design can be thoroughly verified so that all possible data transfer combinations can be exercised within the system. Because many core plus ASIC designs contain on-chip buses, arbitration of these buses with data steering and bridging creates a significant opportunity for design errors. Therefore, typically many tests are created to ensure that the logic designs maintain data integrity. The data that is used to test the system is either manually selected or generated by a software program written by the simulation designer. The data to be used in the tasks must be generated, and synchronized, because data transfers between data sources and the data targets need not be serialized. The designer generating the data must know when and how data will be transferred within the system, before the test data are generated. This data selection process is very time consuming and error-prone. Consequently, there is a need in the art for mechanisms which allow for the automatic generation and checking of data within a hardware system simulation.
The aforementioned needs are addressed by the present invention. Accordingly, there is provided, in a first form, a simulation data verification method. The method generates a first pseudorandom data value in response to a first decoded instruction, wherein a first portion of a seed value comprises an instruction address operand of the first instruction. The first pseudorandom data value is communicated on a first data bus. A second pseudorandom data value is generated in response to a receipt of the first pseudorandom data value and the seed value; and the first and second pseudorandom data values are compared.
There is also provided, in a second form, a data processing system. The system includes circuitry operable for generating a first pseudorandom data value in response to a first decoded instruction, wherein a first portion of a seed value comprises an instruction address operand of the first instruction. Also included is circuitry operable for communicating the first pseudorandom data value on a first data bus, circuitry operable for generating a second pseudorandom data value in response to a receipt of the first data value from the communicating step and the seed value, and circuitry operable for comparing the first and second pseudorandom data values.
Additionally, there is provided, in a third form, a computer program product operable for storage on a program storage medium, the program product includes programming that generates a first pseudorandom data value in response to a first decoded instruction, wherein a first portion of a seed value comprises an instruction address operand of the first instruction. Communications programming transfers the first pseudorandom data value on a first data bus. The program product also has programming and generates a second pseudorandom data value in response to a receipt of the first data value communicated by the aforesaid programming, and the seed value, a well as programming for comparing the first and second pseudorandom data values.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.